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Date: Tue, 15 Oct 1996 12:33:40 +0000 (GMT)
From: BRASH DTN 830-6163 <brash@AM.RDGENG.REO.mts.dec.com>
Subject: Re: STM^ Problem....generic problem description and fix
In-reply-to: <G202028C414OCT199616231719@valmts.vbe.dec.com>
To: Mike Stephens <mstephens>, Joe Barrett <joe.barrett@armltd.co.uk>,
        David Jaggar <dave.jaggar@armltd.co.uk>, Sophie Wilson <swilson>
Cc: Anthony Berent <"anthony berent"@REO.mts.dec.com>,
        David Rusling <"david rusling"@REO.mts.dec.com>,
        Michael Quinn <"michael quinn"@REO.mts.dec.com>,
        Neal Crook <"neal crook"@REO.mts.dec.com>,
        Sean Reynolds <"sean reynolds"@REO.mts.dec.com>
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11-Oct-1996

The SA110 with ID register (CP15 Register 1)
revision less than 3 have a bug in User Register Store Multiple
instruction (STM^). This is the PRIVILEGED MODE STM that is used to store 
user mode registers while in a privileged mode. If the STM^ is executed
while a data cache fill is completing the store address for all but the 
first register may be wrong. 

This is fix in the SA110 revision 3 and the following software work around
can be used on revision 2 parts. Precede the STM^ with 
any of the following, a store that is not a STM^, a MCR, or an MRC. 
Note a "MCR P15, 0, r0, c0, c0, 0", which is a write to the ID register
and on the SA110 is a NOP will fix the problem and uses no registers, 
nor does any writes to memory. 


